- Quartus modelsim altera add internal signals to output verification#
- Quartus modelsim altera add internal signals to output code#
In the right of the main interface, find Installed IP > Library > Basic Functions > Arithmetic > LPM_MULT IP. 1 Set EDA toolĪdd PLL, set the clock input frequency is 50 MHz, and the output is 100 MHz Observe the calculation result on 4 segment decoders.ĭifferent from what we did before, we use EDA simulation. The first input is 8-bit switch, and the second input is the output of an 8-bit counter. Old Version (2019) 6.1 Experiment ObjectiveĨ×8 multiplier. The upper four digits are one number, the lower fourth digits are a number, and the two numbers are multiplied to output the result. Try to use the switch as the input to the multiplier. See Figure 6.23īecause the result of the operation will be one clock cycle later than the input, the multiplier and the result will differ by one line, which does not seem to match, but does not affect the analysis of the experimental results.įigure 6.23 Text displays operation result Summary and Reflection See Figure 6.22.Īfter a certain delay, outputs will display in Transcript. Repeat previous step, to start ModelSim to simulate. Click OK (three times) to finish the setting.
Make the name be consistent with tb file. In Compile test bench, click Test Benches to add tb simulation file.
Set the testbench file: Assignments > Settings.This simulation stops after 1000 clock cycles.Īfter the compilation, the testbench file is added to the ModelSim for simulation, the specific steps are as follows: When writing the testbench file, first mark the time unit of the simulation at the beginning, this experiment is 1 ns, then instantiate the project that needs to be simulated into the testbench file, define the clock cycle and the simulation conditions, and stop the simulation after a certain time. $monitor ("%d * %d = %d", count, sw, mult_res) Define the clock required for the simulation and display the results in text form S1 is the instance of simulation module Method 2: Write a testbench file for simulation Since waveform editing efficiency is relatively low, the use of simulation testbench file is encouraged.
Quartus modelsim altera add internal signals to output code#
The revised code is as follows: module pll_sys_rst( Use external rst signal to provide reset.In Figure 6.16, before PLL starts to lock, the sys_clk already has a rising edge, so PLL_locked signal is just converted from low to high.Add pll_locked signal to the wave, and re-simulate.Counter count does not have a valid result, instead, unknow result XXXXXX is gotten.Click the Run icon to run the simulation. In the tool bar, set the simulation time to be 100 ns. Logical signals select Force and select Clock for clock signals.Set the signals in Wave, right click any signal and a selection window will occur.In the Objects window, choose all the signals and drag them to Wave window.See Figure 6.8.įigure 6.8 Choose the project to simulate Under Design tag, choose simulation project mult_sim and click OK.In the popup window, add libraries under Libraries tag.Tools > Run Simulation Tool > RTL Simulation to start simulation.Click the menu bar Tools > Options, as shown in Figure 6.5, click OK.Method 1: Simulation based on waveform input Here, ModelSim simulation is used to verify the experiment.
Quartus modelsim altera add internal signals to output verification#
) 6.4 Use of ModelSim and the Experiment Verification
Since the simulation tools and the new IP core are used here, there is no introduction or design part of hardware. Oberseve the calculation results with a four-digit segment display.8×8 multiplier, the first input value is an 8-bit switch, and the second input value is the output of an 8-bit counter.Use ModelSim simulation to design output.Experiment 6 Use of Multipliers and ModelSim Simulation 6.1 Experiment Objective